1. Field of the Invention
The present invention relates to a method of checking electronic units mounted in a vehicle, e.g., a car. The invention also concerns a system for performing the above method.
2. Description of Background Information
Recent years have witnessed a remarkable development in the field of motor vehicle electronics. At the same time, electronic units mounting on board vehicles now call for larger scale circuitry. Microcomputer chips (e.g., microprocessors or microcontrollers) 2 are now thus commonly mounted into vehicle-mounted electronic units 1 (note FIG. 1). Such a microcomputer chip 2 can function as a controller unit operative on various controlled systems (not shown in the figures).
Such a microcomputer chip 2 typically includes programs for proper car functioning, and programs specifically developed for internal checking. When it is operational in the vehicle, the programs for vehicle control functions are launched, whereas when circuits are to be inspected, the checking programs for checking are started.
When the vehicle is running, the programs for checking must be prevented from starting. For this purpose, the checking programs are designed such that they can be started only by inputting complex logic combinations at the microcomputer, the combination being chosen such that it does not occur during normal operation. For instance, if an ignition key is not inserted into an ignition socket, an ignition switch would not be expected to be turned in the car. Accordingly, the programs for checking may be designed so that they can start only when a detection signal for the inserted ignition key is active and the ignition switch is also turned on (i.e., the ignition key is inserted and rotated). In this manner, the programs for checking may not be triggered while the car is running. As shown in FIG. 1, an order signal may indicate e.g., that both the signal for detecting the inserted ignition key and the ignition switch are turned on. The signal order thus gives instruction to a test routine, and is delivered from a test device 3 to an ignition input circuit 4 (IG input circuit) contained in an electronic unit 1 for cars. The test device 3 may e.g., be a system for testing at the factory before shipment. Subsequently, the microcomputer chip 2 functions according to a program specific to a test to be performed. The microcomputer chip 2 then returns a response signal to the test device 3 via an output circuit e.g. a courtesy lamp driving circuit (courtesy LP driving circuit) 5. The test device 3 can thus perform function tests, so as to determine whether the microcomputer chip 2 functions well and the input and output circuits work normally. Various input circuits, such as an ignition input circuit 4, and output circuits such as a courtesy lamp driving circuit 5, are commonly used in car electronic units. Consequently, these common circuits require no other specific equipment for testing.
The above test method employs a serial communications system including the test device 3 as a master system and the electronic unit 1 as a slave system. As shown in FIG. 2, communications are periodically sent from the test device 3 to the electronic unit 1 at a rate of 200 ms, irrespective of the presence or absence of an order (i.e., an instruction indicating whether a car-running program or a test program is launched). When an order is effectively to be given, an order signal 7 is loaded on a periodically passing communication. When an initial state (i.e., both the car-running programs and the test programs are put to rest) is to be maintained, an order signal indicating xe2x80x9cno referencexe2x80x9d is sent. When the order signal 7 is given, the microcomputer chip 2 is designed so as to output a response signal 8 after a processing time of tm (within the limit of 10 ms).
The tests for the functioning of the electronic unit 1 are thus performed by using a test device 3, and carried out at the last step of the production process for the car electronic unit 1. The larger the scale of the circuits in the electronic unit 1, the greater is the test time. Therefore, although the serial communication system is applied, the processing time for the electronic unit 1 tends to increase, and creates a production problem.
FIGS. 3 and 4 show signal formats used in communications protocols in a known periodically performed transmission. Specifically, FIG. 3 shows a format for order signal sent from the test device 3 to the electronic unit 1, whereas FIG. 4 shows a format for response signal sent from the electronic unit 1 to the test device 3.
In the above two figures, reference ID indicates 8 bit data (B7xcx9cB0) giving orders, the contents of which are explained in Table 1.
In the above table, the common ports signify the ports common for input and output. The A/D ports signify analog/digital ports, through which voltages are measured, converted into digital terms and read out. The W/D pulses (watchdog pulses) are generated by integrated circuits provided beside the microcomputer, and watch out for malfunctions in the microcomputer.
The data contained in the formats shown in FIGS. 3 and 4 define order contents, as explained below. When ID contains digits xe2x80x9c0000 0000xe2x80x9d (xe2x80x9c00xe2x80x9d in the hexadecimal code), no test is performed. When ID contains digits xe2x80x9c0000 0001xe2x80x9d (xe2x80x9c01xe2x80x9d, ibid.), checksum values (C/S) calculated by the microcomputer chip 2 are requested to be returned. When ID contains digits xe2x80x9c0000 0010xe2x80x9d (xe2x80x9c02xe2x80x9d, ibid.), the input data concerning a switch (SW) for common port are read out. When ID contains digits xe2x80x9c0000 0011xe2x80x9d (xe2x80x9c03xe2x80x9d, ibid.), the data at A/D ports are read-out. When ID contains digits xe2x80x9c0000 0100xe2x80x9d (xe2x80x9c04xe2x80x9d, ibid.), the output from a common port is written-in. When ID contains digits xe2x80x9c0000 0101xe2x80x9d (xe2x80x9c05xe2x80x9d, ibid.), the periodicity of W/D pulses is modified. When ID contains digits xe2x80x9c1111 1111xe2x80x9d (xe2x80x9cFFxe2x80x9d, ibid.), the test mode is terminated.
In FIGS. 3 and 4, reference xe2x80x9cDATA 1xe2x80x9d stores data designating port numbers.
For instance, when reading out the data regarding switch input for common ports (when ID is xe2x80x9c0000 0010xe2x80x9d in Table 1), DATA 1 includes 8-bit data which designate a port, from which the state on switch input are read out. When reading out data from A/D ports (when ID is xe2x80x9c0000 0011xe2x80x9d in Table 1), DATA 1 includes 8-bit data which designate a port, from which A/D values are read out. When writing-in output from common ports (when ID is xe2x80x9c0000 0100xe2x80x9d in Table 1), DATA 1 includes 8-bit data which designate a port, from which the output is written in.
Further in FIGS. 3 and 4, DATA 2 and DATA 3 are supplied with different data, depending on test contents.
When reading out information on switch input for common ports (when ID is xe2x80x9c0000 0010xe2x80x9d in Table 1), an order signal shown in FIG. 3 does not use DATA 2, so that all 8 bits of DATA 2 are supplied with a bit xe2x80x9c0xe2x80x9d (FIG. 5). In a response signal (FIG. 4) to such an order signal, DATA 2 is supplied, bit by bit, with a high-level/a low-level state of each of 8 terminals No. 0 to 7 contained in the port, which is designated by xe2x80x9cDATA 1xe2x80x9d for reading out the state on switch input (see FIG. 6). In the eight bits of xe2x80x9cDATA 2xe2x80x9d in FIG. 6, terminal No. 0 corresponds to the lowest bit level, while terminal No. 7 corresponds to the highest bit level. For instance, the port from which the input state regarding the switch is read out may be allocated port No. 1 (xe2x80x9c0000 0001xe2x80x9d), and only terminal No. 0 of this port may be put in a high state. Then, xe2x80x9cDATA 1xe2x80x9d of the response signal is defined by bits xe2x80x9c0000 0001xe2x80x9d, and xe2x80x9cDATA 2xe2x80x9d is defined by bits xe2x80x9c0000 0001xe2x80x9d. Likewise, the port, from which the input state regarding the switch is read out, may be allocated port No. 3 (xe2x80x9c0000 0011xe2x80x9d), and only terminal No. 1 in this port may be put in a high state. Then, xe2x80x9cDATA 1xe2x80x9d of the response signal is defined by bits xe2x80x9c0000 0011xe2x80x9d, while xe2x80x9cDATA 2xe2x80x9d thereof is defined by bits xe2x80x9c0000 0010. xe2x80x9cDATA 3xe2x80x9d of the response signal of FIG. 6 is not used, so that all the bits thereof are supplied with a bit xe2x80x9c0xe2x80x9d.
Further, when reading-out data from A/D ports (when ID is xe2x80x9c0000 0011xe2x80x9d in Table 1), xe2x80x9cDATA 1xe2x80x9d in the order signal of FIG. 3 designates a port from which A/D values are read out. Likewise, xe2x80x9cDATA 2xe2x80x9d designates a terminal from which A/D values are read-out (FIG. 7). In xe2x80x9cDATA 2xe2x80x9d, terminal No. 0 corresponds to the lowest bit level, while terminal No. 7 corresponds to the highest bit level. For instance, the port from which A/D values are read out has port No. 1 (xe2x80x9c0000 0001), and only the A/D values of terminal No. 0 in this port are read out. Then, xe2x80x9cDATA 1xe2x80x9d of the order signal is housed with bits xe2x80x9c0000 0001xe2x80x9d, while xe2x80x9cDATA 2xe2x80x9d thereof is defined by bits xe2x80x9c0000 0001xe2x80x9d. In another example, the port from which A/D values are read out has port No. 3 (xe2x80x9c0000 0011xe2x80x9d), and only the A/D values of terminal No. 1 in this port are read out. Then, xe2x80x9cDATA 1xe2x80x9d of the order signal is defined by bits xe2x80x9c0000 0011xe2x80x9d, while xe2x80x9cDATA 2xe2x80x9d thereof is defined by bits xe2x80x9c0000 0010xe2x80x9d. The same can be said for xe2x80x9cDATA 2xe2x80x9d of the response signal of FIG. 8, corresponding to the order signal of FIG. 7. Furthermore, xe2x80x9cDATA 3xe2x80x9d in the response signal of FIG. 8 is defined by 8-bit A/D values, which are read out from the terminal designated by xe2x80x9cDATA 2xe2x80x9d, the terminal being included in the port designated by xe2x80x9cDATA 1xe2x80x9d.
Further, when writing in from the output from common ports (when ID is xe2x80x9c0000 0100xe2x80x9d in Table 1), xe2x80x9cDATA 2xe2x80x9d in the order signal of FIG. 3 is defined by an 8-bit content, which is intended to be written into the microcomputer chip 2 (see FIG. 9). In the response signal of FIG. 4 to such order signal, xe2x80x9cDATA 2xe2x80x9d of FIG. 10 is supplied with 8-bit data written in to the microcomputer chip 2 and outputted. In the same response signal of FIG. 10, xe2x80x9cDATA 3xe2x80x9d is not used, so that all the bits thereof are stored with a bit xe2x80x9c0xe2x80x9d.
Reference xe2x80x9cC/Sxe2x80x9d in FIGS. 3 to 10 signifies check sum data. In the order signals shown in FIGS. 12, 14, 16 and 18, items xe2x80x9cIDxe2x80x9d, xe2x80x9cDATA 1xe2x80x9d and xe2x80x9cDATA 2xe2x80x9d are added, and the resulting lowest 8 bit data (i.e., value excluding the figures overflowing from 8 bits) are stored. In the response signals (FIGS. 13, 15, 17 and 19), items xe2x80x9cIDxe2x80x9d, xe2x80x9cDATA 1xe2x80x9d, xe2x80x9cDATA 2xe2x80x9d and xe2x80x9cDATA 3xe2x80x9d are added, and the resulting lowest 8 bit data are stored.
As can be understood from the foregoing past practice, all data covering xe2x80x9cIDxe2x80x9d and xe2x80x9cDATA 1xe2x80x9d to xe2x80x9cDATA 3xe2x80x9d are processed as 8-bit data. Accordingly, one frame of order signal (FIGS. 12, 14, 16 or 18) could process only one port for reading out the input state regarding the switch, one terminal for reading out the A/D values and one port for writing in from the output of common ports. Likewise, one frame of the response signals (FIGS. 13, 15, 17 and 19) could process only for the same number of terminal and ports as in the corresponding order signals. If one frame of order signal or response signal can handle a greater number of ports and terminals, the processing time may be minimized. Such a system configuration will then better cope with an ever increasing circuit scale of electronic units.
One object of the present invention is therefore to provide a method of testing a vehicle mounted electronic unit, in which one frame of order signal and one frame of response signal can process a greater number of ports and terminals, so that the overall processing time can be reduced.
To this end, there is provided a method of testing an electronic unit mountable in a vehicle, the method utilizing a test device and a controller unit included in the electronic unit, an order signal being supplied from the test device to the controller unit, and processed therein to give processed results; the latter being returned from the controller unit to the test device as a response signal. The above method includes providing, in the test device, first data designating several ports and several terminals contained in the controller unit, as well as second data instructing an order content relative to each of the ports and terminals, and providing the first and second data in a frame of order signal, thereby formulating an order signal containing order contents; periodically transmitting the order signal from the test device to the controller unit, frame by frame, at a given frequency; processing the order contents corresponding to each of the ports and terminals contained in the order signal, when the order signal is received by the controller unit, thereby obtaining processed results; providing, in the controller unit, the processed results for each of the ports and terminals in a frame of response signal; and periodically returning the response signal from the controller unit to the test device, frame by frame, at the given frequency.
Preferably, the second data have a data length of 4 bits.
Preferably yet, the first data have a data length of 4 bits.
Typically, providing the first data includes providing an order signal containing third data designating a single port and having a data length of 4 bits, and several terminals, as well as fourth data instructing an order content relative to each of the terminals, and providing first and second data further includes providing said third and fourth data in a frame of order signal.
In the above method, the providing the processed results includes providing a response signal containing the same data as the first and second data in the order signal.
The invention further concerns a system for testing an electronic unit mountable in a vehicle, the system containing a test device and a controller unit included in the electronic unit, an order signal being supplied from the test device to the controller unit, and processed therein to give processed results; the latter being returned from the controller unit to the test device as a response signal. The above system includes a first device that provides, in the test device, first data designating several ports and several terminals contained in the controller unit, as well as second data instructing an order content relative to each of the ports and terminals, and that provides the first and second data in a frame of order signal, such as to formulate an order signal containing order contents; a transmitter that periodically transmits the order signal from the test device to the controller unit, frame by frame, at a given frequency; a processor that processes the order contents corresponding to each of the ports and terminals contained in the order signal, when the order signal is received by the controller unit, such as to obtain processed results; a second device that provides, in the controller unit, the processed results for each of the ports and terminals in a frame of response signal; and a third device that periodically returns the response signal from the controller unit to the test device, frame by frame, at the given frequency.
Preferably, the second data in the first device have a data length of 4 bits.
Preferably yet, the first data in the first device have a data length of 4 bits.
Suitably, the first device includes an order signal provider that provides an order signal containing third data designating a single port and having a data length of 4 bits, and several terminals, as well as fourth data instructing an order content relative to each of the terminals, and the order signal provider further includes a signal provider that provides the third and fourth data in a frame of order signal.
Typically, the second device has a response signal provider that provides a response signal containing the same data as the first and second data in the order signal.